EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 168
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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5–52
Figure 5–43. Dynamic Phase Shifting Waveform
Stratix IV Device Handbook Volume 1
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
f
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1000 MHz and the output clock frequency is 100 MHz,
performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in
shifting the output clock by 180°, which is a phase shift of 5 ns.
The PHASESTEP signal is latched on the negative edge of SCANCLK. In
shown by the second SCANCLK falling edge. PHASESTEP must stay high for at least two
SCANCLK cycles. On the second SCANCLK rising edge after PHASESTEP is latched (the
fourth SCANCLK rising edge in
PHASECOUNTERSELECT are latched and the PLL starts dynamic phase-shifting for the
specified counter(s) and in the indicated direction. On the fourth SCANCLK rising edge,
PHASEDONE goes from high to low and remains low until the PLL finishes dynamic
phase-shifting. You can perform another dynamic phase shift after the PHASEDONE
signal goes from low to high.
Depending on the VCO and SCANCLK frequencies, PHASEDONE low time may be greater
than or less than one SCANCLK cycle.
After PHASEDONE goes from low to high, you can perform another dynamic phase shift.
PHASESTEP pulses must be at least one SCANCLK cycle apart.
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer
to the
Guide.
Phase-Locked Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User
a
t
CONFIGPHASE
b
PHASEDONE goes low synchronous with SCANCLK
Figure
5–43), the values of PHASEUPDOWN and
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
c
d
February 2011 Altera Corporation
Figure
PLLs in Stratix IV Devices
5–43, this is
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