EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 580
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–136
Table 1–49. Power State Functions and Descriptions
Figure 1–113. Power State Transition from the P0 to P2 Power State
Stratix IV Device Handbook Volume 2: Transceivers
Power State
P0s
P0
P1
P2
pipephydonestatus
1
powerdn[1:0]
powerdn
Parallel
2’b00
2’b01
2’b10
2’b11
Clock
The PCIe specification provides the mapping of these power states to the LTSSM
states specified in the PCIe Base Specification 2.0. The PHY-MAC layer is responsible
for implementing the mapping logic between the LTSSM states and the four power
states in the PCIe-compliant PHY.
The PCIe interface in Stratix IV GX and GT transceivers provides an input port,
powerdn[1:0], for each transceiver channel configured in PCIe mode.
mapping between the logic levels driven on the powerdn[1:0] port and the resulting
power state that the PCIe interface block puts the transceiver channel into.
When transitioning from the P0 power state to lower power states (P0s, P1, and P2),
the PCIe specification requires the physical layer device to implement power saving
measures. Stratix IV GX and GT transceivers do not implement these power saving
measures except putting the transmitter buffer in electrical idle in the lower power
states.
The PCIe interface block indicates successful power state transition by asserting the
pipephydonestatus signal for one parallel clock cycle as specified in the PCIe
specification. The PHY-MAC layer must not request any further power state
transition until the pipephydonestatus signal has indicated the completion of the
current power state transition request.
Figure 1–113
state.
Transmits normal data, transmits electrical idle, or
enters into loopback mode
Only transmits electrical idle
Transmitter buffer is powered down and can do a
receiver detect while in this state
Transmits electrical idle or a beacon to wake up the
downstream receiver
2'b00 (P0)
shows an example waveform for a transition from the P0 to P2 power
Function
2'b11 (P2)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Normal operation mode
Low recovery time saving state
High recovery time power saving
state
Lowest power saving state
February 2011 Altera Corporation
Description
Transceiver Block Architecture
Table 1–49
lists
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