EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 296
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX530HH35C2N PDF datasheet #7
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8–18
Figure 8–12. Receiver Block Diagram
Notes to
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Differential I/O Termination
8–12:
10
The Stratix IV device family provides a 100-Ω, on-chip differential termination option
on each differential receiver channel for LVDS standards. On-chip termination saves
board space by eliminating the need to add external resistors on the board. You can
enable on-chip termination in the Quartus II software Assignment Editor.
On-chip differential termination is supported on all row I/O pins and dedicated clock
input pins (CLK[0,2,9,11]). It is not supported for column I/O pins, dedicated clock
input pins (CLK[1,3,8,10]), or the corner PLL clock inputs.
Figure 8–13
Figure 8–13. On-Chip Differential I/O Termination
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows device on-chip termination.
(Note
IOE
2
Left/Right PLL
Transmitter
1),
LVDS
3
(2)
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
rx_outclk)
diffioclk
Z
Z
rx_inclock
0
0
= 50 Ω
= 50 Ω
8 Serial LVDS
Clock Phases
Synchronizer
Receiver with On-Chip
DOUT DIN
Stratix IV Differential
100 Ω Termination
R
D
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
February 2011 Altera Corporation
DPA Circuitry
DPA Clock
Retimed
Data
DIN
Differential Receiver
LVDS Clock Domain
DPA Clock Domain
+
rx_in
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