EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 447

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Overview
Figure 1–1. Example of a Transceiver Block
February 2011 Altera Corporation
Transceiver Block
Transceiver Block
ATX PLL Block
Calibration Block
Calibration Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
GXBL1
GXBL0
8
9
9
Figure 1–1
Links to the corresponding transceiver architecture descriptions are listed below. This
is an elementary diagram and does not represent an actual transceiver block.
Descriptions for the example transceiver architecture are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
Calibration Block
Calibration Block
“Transceiver Block Architecture” on page 1–16
“Transceiver Channel Architecture” on page 1–17
“Transmitter Channel Datapath” on page 1–19
“Transmitter Local Clock Divider Block” on page 1–39
“Receiver Channel Datapath” on page 1–40
“CMU Channel Architecture” on page 1–100
“Loopback Modes” on page 1–190
“Auxiliary Transmit (ATX) PLL Block” on page 1–195
ATX PLL Block
Transceiver Block
Transceiver Block
GXBR1
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
GXBR0
shows an example of the Stratix IV GX and GT transceiver architecture.
8
9
9
Unit (CCU)
Central
Control
Local Clock Divider Block
Transceiver Channel 2
Transceiver Channel 3
1
Transceiver Block
BIST
Transceiver Channel 0
BIST
Transceiver Channel 1
BIST
BIST
10
10
10
10
Loopback
Loopback
Loopback
Loopback
CMU1 Channel
CMU0 Channel
Stratix IV Device Handbook Volume 2: Transceivers
7
7
2
7
1
2
7
2
2
4
6
6
Receiver Channel Datapath
Transmitter Channel Datapath
5
3
1–3