EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 870
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–24
Stratix IV Device Handbook Volume 2: Transceivers
1
1
Whenever a .mif is applied to a channel, the PMA controls for that channel are set to
the default settings chosen in the ALTGX instance used for .mif generation.
The equalization settings of the receiver cannot be modified by a .mif.
Reduced .mif Reconfiguration
This mode is available only for the .mif-based transceiver channel reconfiguration
modes.
This is an optional feature that allows faster reconfiguration and faster simulation
time. For example, if you intend to make minor changes to the transceiver channel,
this might involve a change of only a few words in the .mif.
Here is an example of changing only the termination setting:
■
■
■
■
■
■
Browse to the project directory where you have the Quartus II software installed. For
example, altgx_diffmifgen.exe is available in the following path:
\altera\91\quartus\bin
The syntax for using this .exe is as follows:
\altera\91\quartus\bin\altgx_diffmifgen.exe <a.mif> <b.mif>
That is executed in the project directory with the .mifs. The altgx_diffmifgen.exe
requires two or more ALTGX .mifs.
Channel and CMU PLL Reconfiguration Mode Details
Use this dynamic reconfiguration mode to reconfigure a transceiver channel to a
different functional mode and data rate. To reconfigure a channel successfully, select
the appropriate options in the ALTGX MegaWizard Plug-In Manager (described in
the following sections) and generate a .mif. Connect the ALTGX_RECONFIG instance
to the ALTGX instance. The dynamic reconfiguration controller reconfigures the
transceiver channel by writing the .mif contents into the channel.
Assume that the only word difference is word address 32.
Instead of loading the entire .mif, you can use altgx_diffmifgen.exe to generate a
new .mif. This new .mif only has the modified words.
The new .mif is 22 bits wide, compared with the 16 bits wide in the regular .mif.
There are 6 bits of address in addition to 16 bits of data.
<addr 6 bits> <data 16 bits>
Enable the Use 'reconfig_address' to input address from the MIF in reduced MIF
reconfiguration option in the Channel and TX PLL Reconfiguration screen of the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
Use the reconfig_data[15:0] port to connect the 16 bits of data from the new
.mif.
Use the reconfig_address[5:0] port to connect the 6 bits of address from the new
.mif.
Using altgx_diffmifgen.exe
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
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