EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 276
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–56
Document Revision History
Table 7–21. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
March 2010
Date
Version
Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2)
Table 7–21
3.2
3.1
■
■
■
■
■
■
■
■
■
■
■
■
■
■
34..36
Updated
Added
Updated
Removed Table 7-1 and Table 7-6.
Applied new template.
Minor text edits.
Updated Figure 7–8, Figure 7–11, Figure 7–23, Figure 7–24, Figure 7–29, Figure 7–31,
and Figure 7–36.
Added Figure 7–9 and Figure 7–12.
Added Table 7–7.
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–6, Table 7–8 and Table 7–19.
Added note to the “Memory Interfaces Pin Support” section.
Changed “DLL1 through DLL4” to “DLL0 through DLL3” throughout.
Added frequency mode 7 throughout.
Minor text edits.
Bit
37
38
39
40
41
42
43
44
45
lists the revision history for this chapter.
Table
Table
Figure
7–12.
7–5,
7–36.
Table
7–6,
Table
7–11,
Chapter 7: External Memory Interfaces in Stratix IV Devices
enadqsenablephasetransferreg
Changes
enaoutputphasetransferreg
enainputphasetransferreg
dqsenablectrlphaseinvert
enaoctphasetransferreg
resyncinputphaseinvert
octdelaysetting2[0..2]
dqsoutputphaseinvert
dqoutputphaseinvert
Table
enadataoutbypass
Bit Name
7–19, and
Table
February 2011 Altera Corporation
7–20.
Document Revision History
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