EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 451
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
February 2011 Altera Corporation
Figure 1–4
EP4SGX530 Stratix IV GX device that has 24 and 36 transceiver channels and the
remaining Stratix IV GX devices that have 48 transceiver channels.
Figure 1–4. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 48 Stratix IV GX
Transceiver Channels and EP4SGX530 with 24, 36, and 48 Stratix IV GX Transceiver Channels
Notes to
(1) The 6G ATX PLL R1 and L1 blocks are not available in the EP4SGX530KF40 devices.
(2) Only the EP4SGX530 device in the six transceiver block package has four PCI hard IP blocks.
Figure
shows transceiver channel, PLL, and PCIe hard IP block locations in each
1–4:
EP4SGX290NF45, EP4SGX360NF45, EP4SGX530NF45
EP4SGX530KF43,
EP4SGX530KF40
(1),
Transceiver Block GXBL2
Transceiver Block GXBL2
Transceiver Block GXBL0
(2) (36 transceivers)
Transceiver Block GXBL1
ATX PLL L1 (6G) (1)
EP4SGX530HH35
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL L0 (6G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
(24 transceivers)
(48 transceivers)
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR2
ATX PLL R1 (6G) (1)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL R01 (6G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 1
Channel 0
Channel 3
Channel 2
Channel 3
Channel 2
Channel 1
Channel 0
1–7
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