EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 249

IC STRATIX IV FPGA 530K 1152HBGA

EP4SGX530HH35C2N

Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
DQS Phase-Shift Circuitry
f
1
Stratix IV devices are rich with features that allow robust high-performance external
memory interfacing. The ALTMEMPHY megafunction allows you to use these
external memory interface features and helps set up the physical interface (PHY) best
suited for your system. This section describes each Stratix IV device feature that is
used in external memory interfaces from the DQS phase-shift circuitry, DQS logic
block, leveling multiplexers, and dynamic OCT control block.
The ALTMEMPHY megafunction and the Altera memory controller MegaCore
functions can run at half the frequency of the I/O interface of the memory devices to
allow better timing management in high-speed memory interfaces. Stratix IV devices
have built-in registers in the IOE to convert data from full-rate (the I/O frequency) to
half-rate (the controller frequency) and vice versa. You can bypass these registers if
your memory controller is not running at half the rate of the I/O frequency. When
using the Altera memory controller MegaCore functions, the ALTMEMPHY
megafunction is instantiated for you.
For more information about the ALTMEMPHY megafunction, refer to the
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Stratix IV phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions when the DQS/CQ and CQn pins are acting as input clocks or
strobes to the FPGA. The DQS phase-shift circuitry consists of DLLs that are shared
between multiple DQS pins and the phase-offset module to further fine-tune the DQS
phase shift for different sides of the device.
Stratix IV Device Handbook Volume 1
Guide.
External
®
7–29

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