EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1125
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices
April 2011 Altera Corporation
OTL 4.10 (1),
Total Jitter at
11.18 Gbps
Deterministic
Jitter
Sinusoidal Jitter
tolerance
Notes to
(1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
(2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
(3) Contact Altera for board and link best practices at BER = 1E-15.
Total Transmitter jitter at
11.3 Gbps
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for stated conditions only.
(3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
(4) Contact Altera for board and link best practices at BER = 1E-15.
Symbol/Description
Description
characterized was 0.30 UI.
Symbol/
Table
Table
(4)
1–31:
1–32:
(3)
Pattern = PRBS-
31
V
REFCLK =
698.75 MHz
Jitter Frequency
= 40 KHz
Pattern = PRBS-
31
Equalization =
Disabled
BER = 1E-12
Jitter Frequency
≥ 4 MHz
Pattern = PRBS-
31
Equalization =
Disabled
BER = 1E-12
OD
Table 1–32
Conditions
= 800 mV
Pattern = PRBS-31
Vod = 800 mV
REFCLK = 706.25 MHz
12 channels in Basic ×1 mode
lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
Conditions
-1 Industrial Speed Grad
Min
—
—
> 0.05
Typ
> 5
—
—
Max
0.30
0.17
-1 Industrial
Speed Grade
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
0.23 UI
Mean
-2 Industrial Speed Grade -3 Industrial Speed Grade
Min
—
—
(3)
> 0.05
Typ
> 5
—
—
(Note
Speed Grade
-2 Industrial
Mean
1),
—
Max
0.30
0.17
(2)
Min
—
—
Speed Grade
-3 Industrial
Mean
—
Typ
—
—
—
—
0.30
0.17
Max
Unit
UI
1–43
Unit
UI
UI
UI
UI
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