EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 600
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–156
Figure 1–123. Stratix IV GX and GT XAUI Mode Configuration
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
PMA-PCS Interface
Fabric-Transceiver
Encoder/Decoder
Fabric-Transceiver
TX PCS Latency
Interface Frequency
Functional Modes
Low-Latency PCS
RX PCS Latency
Channel Bonding
Data Rate (Gbps)
Rate Match FIFO
Functional Mode
Deskew FIFO
(Pattern Length)
Byte Ordering
Interface Width
Byte SerDes
Word Aligner
8B/10B
FPGA
(MHz)
Width
FPGA
Figure 1–123
devices.
8-bit
Single
Width
10-bit
shows the XAUI mode configuration supported in Stratix IV GX and GT
Basic
16-bit
Double
Width
Stratix IV GX and GT Configurations
20-bit
10-bit
PIPE
10-bit
XAUI
Synchronization
(10-Bit/K28.5/)
State Machine
3.125 - 3.75
Automatic
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
XAUI
156.25-
16-Bit
187.5
4.5 - 6
14.5 -
GIGE
10-bit
x4
Chapter 1: Transceiver Architecture in Stratix IV Devices
18
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
February 2011 Altera Corporation
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
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