EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 947
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Document Revision History
Document Revision History
Table 5–20. Document Revision History (Part 1 of 2)
February 2011 Altera Corporation
February 2011
March 2010
November 2009
June 2009
Date
Version
Table 5–20
3.0
3.2
3.1
2.1
■
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■
■
■
■
■
■
■
■
■
■
■
■
■
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Updated
Updated
Updated the
Reconfiguration Mode
Instances”,
and
Removed the “Continuous Mode for a Single Channel” and “Powerdown for a Single
Channel” sections.
Updated chapter title.
Applied new template.
Minor text edits.
Updated Table 5–5, Table 5–6, Table 5–15, Table 5–16, and Table 5–17.
Updated Figure 5–1, Figure 5–14, Figure 5–16, Figure 5–26, and Figure 5–37.
Updated the “Blocks Reconfigured in the Data Rate Division in Transmitter Mode”,
“Logical Channel Addressing of PMA-Only Channels”, “Central Control Unit
Reconfiguration Mode Details”, “EyeQ”, “Error Indication During Dynamic
Reconfiguration”, and “Functional Simulation of the Dynamic Reconfiguration Process”
sections.
Added a note to the “Central Control Unit Reconfiguration Mode Details” section.
Minor text edits.
Completely re-wrote and re-organized chapter.
Updated all graphics and tables.
Updated Figure 5–4, Figure 5–8, Figure 5–9, Figure 5–10, Figure 5–11, Figure 5–15,
Figure 5–22, Table 5–37, Table 5–38, Figure 5–44, Figure 5–47, Figure 5–48,
Figure 5–49, Figure 5–50, Figure 5–51, Figure 5–52, Figure 5–53, and Figure 5–54
Updated Table 5–2 and Table 5–31
Changed “logical_tx_pll_sel[1:0]” to “logical_tx_pll_sel” throughout
Updated “The reconfig_clk Clock Requirements for the ALTGX Instance and
ALTGX_RECONFIG Instance”, “The logical_tx_pll_sel and logical_tx_pll_sel_en Ports”,
“How to Use the logical_tx_pll_sel Port?”, and “When Can the logical_tx_pll_sel and
logical_tx_pll_sel_en Ports be Used?”
Minor text edits
lists the revision history for this chapter.
“Functional Simulation of the Dynamic Reconfiguration Process”
Table
Figure
“One Time Mode for a Single
“Transceiver Channel Reconfiguration Mode
5–5,
5–1.
Table
Details”,
5–6, and
“Connecting the ALTGX and ALTGX_RECONFIG
Table
Changes
5–16.
Channel”,
Stratix IV Device Handbook Volume 2: Transceivers
“Applying a .mif in the User
Details”.
“PMA Controls
sections.
Design”,
5–101
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