EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 733

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–16. Quartus II Assignments
February 2011 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II Assignment Editor.
Table
FPGA Fabric-Receiver Interface Clocking
2–13:
1
Table 2–16
editor.
For more implementation information, refer to
Configuring Sixteen Identical Channels Across Four Transceiver Blocks” on
page
Basic (PMA Direct) mode
In Basic (PMA Direct) mode, each channel must be clocked by its own tx_clkout. As a
result, the number of global and/or regional clock resources required is significantly
higher. In Basic (PMA Direct) ×N mode, to save on global and/or regional clock
resources, you may use tx_clkout from centrally located channels to clock all the
channels. The coreclkout port is not available in Basic (PMA Direct) ×N mode.
The receiver phase compensation FIFO compensates for the phase difference between
the parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO
read clock). The receiver phase compensation FIFO read clock forms the FPGA
fabric-Receiver interface clock. The FIFO write clock and read clock must have exactly
the same frequency (0 PPM frequency difference).
Stratix IV transceivers provide the following two options for selecting the receiver
phase compensation FIFO read clock:
■
■
User-selection is provided to share transceiver datapath interface clocks in order to
reduce the global, regional, and periphery clock resource usage in your design.
Full design hierarchy name of one of the following clock drivers that you choose to drive the
tx_coreclk ports of all identical channels (1):
■
■
■
■
■
■
tx_dataout pins of all identical channels whose tx_coreclk ports are connected together and
driven by the 0 PPM clock driver.
GXB 0 PPM Core Clock Setting
ON
“Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock” on
page 2–62
“User-Selected Receiver Phase Compensation FIFO Read Clock” on page 2–69
tx_clkout
coreclkout
FPGA CLK input pins
Transceiver refclk pins
Clock output from the left and right or top and bottom PLLs
tx_dataout port of one of the identical channels
2–76.
lists the Quartus II assignments that you must make in the assignment
“Configuration Example 2:
Stratix IV Device Handbook Volume 2: Transceivers
2–61