EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 761
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Sharing CMU PLLs
February 2011 Altera Corporation
Table 3–3. ALTGX MegaWizard Plug-In Manager Settings for Example 1
You can force the placement of the transceiver channels to a specific transceiver block
by assigning pins to tx_dataout and rx_datain. Otherwise, the Quartus II software
selects a transceiver bank.
Figure 3–1
combines the transceiver channel instances. Because the RX CDR is not shared
between channels, only the CMU PLL is shown.
Note to
(1) The Specify base data rate option is 4.25 Gbps for all four instances. Given that the CMU PLL bandwidth setting
and input reference clock are the same and that the pll_powerdown ports are driven from the same logic or pin,
the Quartus II software shares a single CMU PLL that runs at 4.25 Gbps.
Table
Instance
inst3
and
3–3:
Figure 3–2
What is the effective data rate?
Specify base data rate
show the scenario before and after the Quartus II software
General Screen Option
Stratix IV Device Handbook Volume 2: Transceivers
Setting (Gbps)
4.25
4.25
(1)
3–7
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