EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 798
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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3–44
Stratix IV Device Handbook Volume 2: Transceivers
Combination Requirements When You Use Multiple TX PLLs
Table 3–19
Instance 2 when you compile the design.
Table 3–19. Assignment for the GXB TX PLL Reconfiguration Group for Instance 2
Key Observations
■
■
■
■
This scenario describes transceiver configurations that have the use additional
CMU/ATX Transmitter PLLs from outside the transceiver block option in the
reconfig screen enabled.
If you create a transceiver instance using the above option and would like to share the
CMU PLLs or ATX PLL with other instances, ensure that you have met the following
requirements:
■
■
To
Assignment Name
Value
The Main PLL in Instance 1 is configured for GIGE data rates because this is the
data rate that you intend to run the first instance.
The main PLL in Instance 2 is configured for SONET OC48 data rates because this
is the data rate that you intend to run the second channel.
Note that the PLL logical reference index values for similar PLLs in Instance 1 and
Instance 2 are the same.
The GXB TX PLL Reconfiguration group setting value for tx_dataout of
Instance 1 and Instance 2 are the same.
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option in other instances.
1
The PLL logical reference index value of the similar PLLs that you intend to
combine must be the same in all the instances considered.
1
Assignment
The number of additional PLLs selected (in the How many additional PLLs
are used option) can be different between instances.
Similar PLLs are the ones that have the same data rate, input clock
frequency, and bandwidth setting.
lists the assignment for the GXB TX PLL Reconfiguration group for
tx_dataout_instance2[1]
You can use any one of the channel port names within this Instance for
this assignment.
GXB TX PLL Reconfiguration group setting
6
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combination Requirements When You Enable Channel Reconfiguration
Setting
February 2011 Altera Corporation
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