EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 705
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–19. Two PCIe ×8 Links in Six Transceiver Block Devices
Notes to
(1) Stratix IV devices with six transceiver blocks allow a maximum of two PCIe ×8 links occupying four transceiver blocks. You can configure the
(2) You can use a ×4 PCIe configuration in either a master or slave block.
February 2011 Altera Corporation
other two transceiver blocks to implement other functional modes.
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
2–19:
Figure 2–19
EP4SGX230KF40, EP4SGX290KF40, EP4SGX360KF40, EP4SGX530KF40
Transceiver Block
Transceiver Block
Transceiver Block
GXBL1 (Slave)
GXBL0(Master)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBL2
shows two PCIe ×8 links in six transceiver block devices.
Second PCIe
x8 Link
First PCIe
x8 Link
(Note 1), (2)
Transceiver Block
Transceiver Block
Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
GXBR0 (Master)
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBR2
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
2–33
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