EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 670
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–226
Document Revision History
Table 1–81. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
March 2010
November 2009
Date
Version
Table 1–80. Reference Information (Part 3 of 3)
Table 1–81
4.0
4.2
4.1
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Applied new template.
Updated the “Overview”,
Coupling for Stratix IV GX and GT
Generation”,
in the Receiver Buffer and Receiver
“Word-Alignment-Based Byte
“Loopback
and
Updated
Figure
Figure
Figure
Figure
Updated
Table
Table
Updated chapter title.
Applied new template.
Minor text edits.
Added two references to the beginning of the chapter.
Updated the “Configuring CMU Channels for Clock Generation” section.
Updated Figure 1–101.
Minor text edits.
Added “Adaptive Equalization (AEQ)”, “EyeQ”, “SATA and SAS Options”, “Deterministic
Latency Mode”, “CPRI and OBSAI”, and “Reference Information” sections.
Added Figure 1–91, Figure 1–93, Figure 1–95, and Figure 1–97.
Added Stratix IV GT device information.
Updated Figures.
Updated Tables.
Re-organized chapter information.
Minor text edits.
Terms Used in this Chapter
lists the revision history for this chapter.
“PCI Express Electrical Gold Test with Compliance Base Board (CBB)”
1–17,
1–43,
1–7,
1–64,
1–97,
1–112, and
Word Aligner
XAUI Mode
Figure
Table
Modes”,
Figure
Table
Table
Figure
“Configuring CMU Channels as Transceiver
Figure
1–2,
1–1,
1–18,
1–45,
Figure
1–8,
Table
1–76,
1–99,
“Reverse Serial
Figure
Figure
Table
Table
“Transceiver Block
1–157.
1–3,
Figure
Figure
1–2,
1–19,
1–68,
Ordering”,
1–9,
Table
Figure
1–83,
1–100,
Devices”,
CDR”,
Figure
Loopback”,
1–4,
Table
Table
Changes
Figure 1–84,Figure
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–3,
Figure
“SATA and SAS
Table
1–21,
1–70,
“Modes of Operation of the
1–10,
“Configuring CMU Channels for Clock
Architecture”,
Figure
1–5,
1–101,
“Input Signals to the Calibration
Table
Table
Figure
1–4,
Useful Reference Points
Table
1–23,
1–74, and
Figure
1–11,
Figure
Channels”,
Options”,
1–13,
“DC-Coupled
1–95,
page 1–153
page 1–59
February 2011 Altera Corporation
Table
Figure
1–105,
1–5,
Table
Table
Figure
1–24,
Document Revision History
“GIGE
“Offset Cancellation
Figure
1–56,
Figure
AEQ”,
1–14,
1–77.
Links”,
1–69,
Table
Mode”.
sections.
1–6,
Figure
1–111,
Table
1–41,
“Link
Block”,
1–57,
1–16,
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