EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 66
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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3–10
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Stratix IV Device Handbook Volume 1
8K × 1
4K × 2
2K × 4
Read Port
Simple Dual-Port Mode
Figure 3–8
mode with unregistered outputs. Registering the RAM’s outputs simply delays the
q output by one clock cycle.
Figure 3–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode
allows you to perform one read and one write operation to different locations at the
same time. Write operation happens on port A; read operation happens on port B.
Figure 3–9
Figure 3–9. Stratix IV Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input/output clock mode in addition to read/write clock mode.
Simple dual-port mode supports different read and write data widths (mixed-width
support).
dual-port mode. MLABs do not have native support for mixed-width operation. The
Quartus II software implements mixed-width memories in MLABs by using more
than one MLAB.
8K × 1
v
v
v
q_a (asyn)
Figure
address
bytenna
data_a
wrena
clk_a
rdena
4K × 2
Table 3–5
v
v
v
shows timing waveforms for read and write operations in single-port
shows a simple dual-port configuration.
3–9:
2K × 4
lists the mixed width configurations for M9K blocks in simple
v
v
v
A123
01
A0 (old data)
1K × 8
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
v
v
v
B456
10
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
A0
D
512 × 16
old
Write Port
v
v
v
D
old
23
C789
00
(Note 1)
B423
256 × 32
rd_addressstall
v
v
v
rdaddress[ ]
ecc_status
rdclocken
DDDD
rdclock
rden
A1(old data)
q[ ]
1K × 9
—
—
—
February 2011 Altera Corporation
A1
EEEE
11
DDDD
512 × 18
—
—
—
FFFF
Memory Modes
EEEE
256 × 36
—
—
—
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