EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 713

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–9. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes Without Rate Matcher
February 2011 Altera Corporation
SONET/SDH OC12
SONET/SDH OC48
HD-SDI
3G-SDI
Functional Mode
Depending on whether you use the byte deserializer or not, the parallel recovered
clock (when you do not use the byte deserializer) or a divide-by-two version of the
parallel recovered clock (when you use the byte deserializer) clocks the write port of
the receiver phase compensation FIFO. This clock is driven directly on the rx_clkout
port as the FPGA fabric-Transceiver interface clock. You can use the rx_clkout signal
to capture the receiver data and status signals in the FPGA fabric.
Table 2–9
modes without rate matcher.
Non-Bonded Receiver Clocking with Rate Matcher
The following functional modes have non-bonded receiver channel configuration
with rate-matcher:
■
■
■
■
1.4835 Gbps
2.488 Gbps
1.485 Gbps
2.967 Gbps
Data Rate
622 Mbps
2.97 Gbps
PCIe ×1
GIGE
Serial RapidIO
Basic with rate matcher
lists the receiver datapath clock frequencies in non-bonded functional
Serial Recovered
Clock Frequency
741.75 MHz
1.4835 GHz
742.5 MHz
1.244 GHz
1.485 GHz
311 MHz
Clock Frequency (MHz)
Parallel Recovered
148.35
77.75
148.5
296.7
311
297
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA Fabric-Transceiver
148.35
(MHz)
77.75
148.5
N/A
N/A
N/A
Deserializer
With Byte
74.175
148.35
(MHz)
155.5
74.25
148.5
N/A
2–41