EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 734

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–62
Stratix IV Device Handbook Volume 2: Transceivers
1
Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock
If you do not select the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager,
the Quartus II software automatically selects the receiver phase compensation FIFO
read clock for each channel in that ALTGX instance. The Quartus II software selects
the FIFO read clock depending on the channel configuration. In non-bonded channel
configurations, the FPGA fabric-receiver interface clocking has two scenarios:
■
■
Non-Bonded Channel Configuration with Rate Matcher
In non-bonded channel configuration, the transceiver channels may or may not be
identical. Identical transceiver channels are defined as channels that have exactly the
same CMU PLL and receiver CDR input reference clock sources, exactly the same
CMU PLL and receiver CDR configuration, and exactly the same PMA and PCS
configuration.
Example 6 assumes channels 0 and 1, driven by the CMU0 PLL in a transceiver block,
are identical. Also, channels 2 and 3, driven by the CMU1 PLL in the same transceiver
block, are identical. In this case, the Quartus II software automatically drives the read
port of the receiver phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the read port of the receiver phase compensation
FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the tx_clkout[0] signal
to latch the receiver data and status signals from channels 0 and 1 in the FPGA fabric.
Use the tx_clkout[2] signal to latch the receiver data and status signals from
channels 2 and 3 in the FPGA fabric.
This configuration uses two FPGA global and/or regional clock resources, one for the
tx_clkout[0] signal and the other for the tx_clkout[2] signal.
Receivers that do not use a rate matcher block (refer to
Clocking Without Rate Matcher” on page
Receivers that use a rate matcher block (refer to
with Rate Matcher” on page
Example 6: Two Groups of Two Identical Channels in a Transceiver Block
2–41)
2–39)
Chapter 2: Transceiver Clocking in Stratix IV Devices
“Non-Bonded Receiver Clocking
FPGA Fabric-Transceiver Interface Clocking
“Non-Bonded Receiver
February 2011 Altera Corporation