EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 611
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–133. GIGE Mode Datapath
Table 1–62. Transceiver Datapath Clock Frequencies in GIGE Mode
February 2011 Altera Corporation
Functional Mode
GIGE
rx_coreclk[0]
tx_coreclk[0]
FPGA
Fabric
FPGA
Fabric-Transceiver
Interface Clock
GIGE Mode Datapath
Figure 1–133
mode.
Table 1–62
8B/10B Encoder
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers
from the transmitter phase compensation FIFO and generates 10-bit encoded data.
The 10-bit encoded data is fed to the serializer. For more information about 8B/10B
encoder functionality, refer to
GIGE Protocol—Ordered Sets and Special Code Groups
Table 1–63
specification.
Table 1–63. GIGE Ordered Sets (Part 1 of 2)
Code
/C1/
/C2/
/C/
Compensation
1.25 Gbps
Data Rate
tx_clkout[0]
RX Phase
FIFO
Compensation
wrclk rdclk
TX Phase
lists the transceiver datapath clock frequencies in GIGE functional mode.
lists ordered sets and special code groups specified in the IEEE 802.3
FIFO
shows the transceiver datapath when configured in GIGE functional
Configuration 1
Configuration 2
8B/10B
Decoder
Configuration
8B/10B
Decoder
Ordered Set
High-Speed Serial
Clock Frequency
625 MHz
Match
FIFO
Rate
“8B/10B Encoder” on page
Transmitter Channel PCS
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Number of Code
Parallel Recovered
8B/10B
Encoder
Parallel Recovered Clock
Parallel Clock
Groups
Low-Speed
Frequency
Clock and
Aligner
Word
125 MHz
—
4
4
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Serializer
Transmitter Channel PMA
De-
De-
Serializer
Clock Divider
/K28.5/D21.5/Config_Reg
/K28.5/D2.2/Config_Reg
1–23.
Local
Interface Clock Frequency
Alternating /C1/ and /C2/
FPGA Fabric-Transceiver
CDR
High-Speed Serial Clock
Encoding
125 MHz
(1)
(1)
1–167
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