EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 483

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–35. Transmitter Local Clock Divider Block
February 2011 Altera Corporation
CMU1 PLL High-Speed Clock
CMU0 PLL High-Speed Clock
f
1
pulse is driven on the pipephydonestatus port and 3'b011 is driven on the pipestatus
port to indicate that a receiver has been detected. There is some latency after asserting
the tx_detectrxloopback signal, before the receiver detection is indicated on the
pipephydonestatus port. For signal timing to perform the receiver detect operation,
refer to
The tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to
the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated.
The Stratix IV GX and GT transmitter output buffers support transmission of PCIe
Electrical Idle (or individual transmitter tri-state). The tx_forceelecidle port puts
the transmitter buffer in Electrical Idle mode. This port has a specific functionality in
each power state. For the signal timing to perform the electrical idle transmission in
PCIe mode, refer to
For more information about using the tx_forceelecidle signal under different power
states, refer to the PCIe specification 2.0.
Transmitter Local Clock Divider Block
Each transmitter channel contains a local clock divider block. It receives the
high-speed clock from the CMU0 PLL or CMU1 PLL and generates the high-speed serial
clock for the serializer and the low-speed parallel clock for the transmitter PCS
datapath. The low-speed parallel clock is also forwarded to the FPGA fabric
(tx_clkout). The local clock divider block allows each transmitter channel to run at
/1, /2, or /4 of the CMU PLL data rate. The local clock divider block is used only in
non-bonded functional modes (for example, GIGE, SONET/SDH, and SDI mode).
Figure 1–35
PCIe Electrical Idle
Figure 1–109 on page
shows the transmitter local clock divider block.
Figure 1–108 on page
÷
1, 2, or 4
÷
n
1–134.
÷
4, 5, 8, or 10
1–133.
Stratix IV Device Handbook Volume 2: Transceivers
Low-Speed
Parallel Clock
High-Speed
Serial Clock
1–39