EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 78
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–22
Stratix IV Device Handbook Volume 1
Power-Up Conditions and Memory Initialization
f
Figure 3–22
behavior for don’t care mode in M9K and M144K blocks.
Figure 3–22. M9K and M144K Blocks Mixed-Port Read-During Write: Don’t Care Mode
Mixed-port read-during-write is not supported when two different clocks are used in
a dual-port RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
M9K memory cells are initialized to all zeros through a default .mif file in the
Quartus II software. However, you may specify your own initialization of the
memory cells through a defined .mif file. M144K memory cells are not initialized and;
therefore, come up in an undefined state. This is to prevent the programming file from
being too large. Again, you may specify your own initialization of the memory cells
through a defined .mif file.
MLABs power up to zero if output registers are used and power up reading the
memory contents if output registers are not used. You must take this into
consideration when designing logic that might evaluate the initial power-up values of
the MLAB memory block. For Stratix IV devices, the Quartus II software initializes
the RAM cells to zero unless there is a .mif file specified.
As mentioned, all memory blocks support initialization using a .mif file. You can
create .mif files in the Quartus II software and specify their use with the RAM
MegaWizard Plug-In Manager when instantiating a memory in your design. Even if a
memory is pre-initialized (for example, using a .mif file), it still powers up with its
outputs cleared.
For more information about .mif files, refer to the
User Guide
q_b_(asyn)
address_a
address_b
clk_a&b
bytenna
data_a
wrena
rdenb
and the
shows a sample functional waveform of mixed-port read-during-write
Quartus II
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11
Handbook.
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
01
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A0
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10
Internal Memory (RAM and ROM)
DDDD
February 2011 Altera Corporation
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11
A1
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Design Considerations
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