EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 937
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 937 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Duration
February 2011 Altera Corporation
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles per channel for each of these controls:
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles per channel for each of these controls. The
data_valid signal is then asserted after the busy signal goes low.
■
■
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles per channel for each of these controls. The
data_valid signal is then asserted after the busy signal goes low.
■
■
Offset Cancellation Duration
When the device powers up, the busy signal remains low for the first reconfig_clk
clock cycle. Offset cancellation control is only for the receiver channels. The
ALTGX_RECONFIG instance takes 18500 reconfig_clk clock cycles per channel for
Receiver only and Receiver and Transmitter channels. It takes 900 reconfig_clk
clock cycles per channel for Transmitter only channels to determine if the channel
under reconfiguration is a receiver channel or not. The ATLGX_RECONFIG requires
an additional 130,000 clock cycles for these values to take effect. The
ALTGX_RECONFIG instance takes approximately two reconfig_clk clock cycles per
channel for the unused logical channels.
To demonstrate offset cancellation duration, consider the following example:
■
■
■
For this example, the ALTGX_RECONFIG instance consumes the following number
of reconfig_clk clock cycles for offset cancellation:
■
■
■
The offset cancellation duration for the ALTGX_RECONFIG instance to reconfigure
the Transmitter only channel, Receiver only channel, non-existent logical channels 1,
2, and 3 = 149,406 cycles (900 +18,500 +6 + 130,000).
tx_preemp_0t (pre-emphasis control pre-tap)
tx_preemp_2t (pre-emphasis control second post-tap)
tx_preemp_1t_out (pre-emphasis control first post-tap)
tx_vodctrl_out (voltage output differential)
rx_eqctrl_out (equalizer control)
rx_eqdcgain_out (equalizer DC gain)
tx_preemp_0t_out (pre-emphasis control pre-tap)
tx_preemp_2t_out (pre-emphasis control second post-tap)
One ALTGX_RECONFIG instance is connected to two ALTGX instances.
ALTGX Instance 1 has one Transmitter only channel (logical_channel_address = 0)
ALTGX Instance 2 has one Receiver only channel (logical_channel_address = 4)
900 cycles for the Transmitter only channel
18,500 cycles for the Receiver only channel
2 cycles each for non-existent channels with logical_channel_addresses = 1, 2,
and 3 and 130,000 cycles as a baseline for the values to take affect.
Read Transaction Duration
Stratix IV Device Handbook Volume 2: Transceivers
5–91
Related parts for EP4SGX530HH35C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: