EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 882

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–36
Figure 5–21. Option 3 for Receiver Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Stratix IV Device Handbook Volume 2: Transceivers
FPGA Fabric
rx_clkout[1]
rx_clkout[0]
Low-speed parallel clock generated by the local divider of the transceiver
High-speed serial clock generated by the CMU0 PLL
High-speed serial clock generated by the CMU1 PLL
Figure 5–21
receiver channels of a transceiver block.
This section describes the ALTGX MegaWizard Plug-In Manager settings related to
the FPGA fabric-transceiver channel interface data width when you select and
activate channel and CMU PLL reconfiguration mode. You must set up the FPGA
fabric-transceiver channel interface data width when functional mode reconfiguration
involves:
■
■
You can set up the FPGA fabric-transceiver channel interface data width by enabling
the Channel Interface option in the Modes screen.
Enable the Channel Interface option if the reconfiguration channel has:
■
■
changes in the FPGA fabric-transceiver channel data width
enables and disables the static PCS blocks of the transceiver channel
changed the FPGA fabric-transceiver channel interface data width
changed the input control signals and output status signals
FPGA Fabric-Transceiver Channel Interface Selection
OR
OR
shows the respective rx_clkout of each channel clocking the respective
Transceiver Block
TX0 (2 Gbps)
TX1 (2 Gbps)
RX0
RX1
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
CMU0 PLL
CMU1 PLL
February 2011 Altera Corporation