EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 704

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–32
Figure 2–18. One PCIe x8 Link in Two Transceiver Block Devices and Two PCIe x8 Links in Four Transceiver Block
Devices
Note to
(1) You can use a ×4 PCIe configuration in either a master or slave block.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
(Note 1)
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
2–18:
Figure 2–18
links in four transceiver block devices.
Transceiver Block GXBL0
EP4SGX290FH29, EP4SGX360FH29, EP4SGX110FF35, EP4SGX230FF35,
EP4SGX290FF35, EP4SGX360FF35, EP4SGX230HF35, EP4SGX290HF35,
EP4SGX360HF35, EP4SGX530HH35
Transceiver Block GXBL1
Two PCIe x8 Links in Four Transceiver Block Devices
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
shows one PCIe ×8 link in two transceiver block devices and two PCIe ×8
Second PCIe
x8 Link
One PCIe x8 Link in Two Transceiver Block Devices
First PCIe
EP4SGX70DF29
EP4SGX110DF29
EP4SGX230DF29
x8 Link
Transceiver Block GXBR1
Transceiver Block GXBR0
Chapter 2: Transceiver Clocking in Stratix IV Devices
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0