EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 988
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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1–30
Figure 1–10. MegaWizard Plug-In Manager Options—Main PLL Screen
Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 1 of 3)
Stratix IV Device Handbook Volume 3
Main Tx PLL/Rx PLL Settings
Use central clock divider to
drive the transmitter
channels using ×4/×N lines
What is the PLL logical
reference index (used in
reconfiguration)?
ALTGX Setting
Figure 1–10
MegaWizard Plug-In Manager.
Table 1–8
Plug-In Manager for your ALTGX custom megafunction variation.
If this option is enabled, the transmitter PLL is outside the
transceiver block. If this option is disabled, the transmitter
PLL is one of the CMU PLLs within the same transceiver
block.
The PLL logical reference index is selected based on the
location of the alternate PLL. If the Use central clock divider
to drive the transmitter channels using ×4/×N lines option is
unchecked this must be 0 or 1, otherwise this must be 2 or 3.
lists the available options on the Main PLL screen of the MegaWizard
shows the options available on the Main PLL screen of the ALTGX
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
February 2011 Altera Corporation
“Selecting the PLL Logical
Reference Index for
Additional PLLs” and the
“Multi-PLL Settings”
sections in the
Reconfiguration in
Stratix IV Devices
“Selecting the PLL Logical
Reference Index for
Additional PLLs” and
“Selecting the Logical
Reference Index of the CMU
PLL” sections in the
Dynamic Reconfiguration in
Stratix IV Devices
Reconfiguration Settings
Reference
Dynamic
chapter.
chapter.
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