EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 990

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–32
Table 1–8. MegaWizard Plug-In Manager Options (Main PLL Screen) (Part 3 of 3)
Stratix IV Device Handbook Volume 3
What is the input clock
frequency?
What is the PLL bandwith
mode?
Create powerdown port to
power down the PLL.
Create locked port to indicate
that the PLL is in lock with
the reference clock.
Use Auxiliary Transmitter
(ATX) PLL (available only if
central clock divider is used)
ALTGX Setting
These settings are to dynamically reconfigure the transceiver
channel to listen to the alternate transmitter PLL.
■
■
The available options are Auto, Low, Medium, and High.
Select the appropriate option based on your system
requirements.
Each transceiver block has two CMU PLLs. Each CMU/ATX
PLL has a dedicated power down signal called
pll_powerdown. This signal powers down the CMU PLL.
Each CMU/ATX PLL has a dedicated pll_locked signal that
is fed to the FPGA fabric to indicate when the PLL is locked to
the input reference clock.
This option is only available for certain data rates. Refer to the
DC and Switching Characteristics for Stratix IV Devices
chapter for the supported data rates.
This option enables the auxiliary transmitter PLL. This is a
low-jitter PLL that resides between the transceiver blocks and
can be used as a transmitter PLL.
If you select the input clock frequency option in the What
would you like to base the setting on? field, the ALTGX
MegaWizard Plug-In Manager displays the list of effective
serial data rates in this field.
If you select the data rate option in the What would you
like to base the setting on? field, the ALTGX MegaWizard
Plug-In Manager allows you to specify the effective serial
data rate value in this field.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
February 2011 Altera Corporation
“CMU PLL Reconfiguration
Mode Details” section in the
Dynamic Reconfiguration in
Stratix IV Devices
“PLL Bandwidth Setting”
section in the
Architecture in Stratix IV
Devices
“User Reset and
Power-Down Signals”
section in the
and Power Down in
Stratix IV Devices
“User Reset and
Power-Down Signals”
section in the
and Power Down in
Stratix IV Devices
“Auxiliary Transmit (ATX)
PLL Block” section in the
Transceiver Architecture in
Stratix IV Devices
and the
Characteristics for Stratix IV
Devices
DC and Switching
chapter.
section.
Reconfiguration Settings
Reference
Reset Control
Reset Control
Transceiver
chapter.
chapter.
chapter.
chapter