EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 680
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–8
Figure 2–5. Termination Scheme for a Reference Clock Signal When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe specification.
(2) Select resistor values as recommended by the PCIe clock source vendor.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
2–5:
f
1
Figure 2–5
configured as HCSL.
Inter-Transceiver Block (ITB) Clock Lines
The refclk0 and refclk1 pins of other transceiver blocks using the ITB clock lines
provide an input reference clock path from the refclk pins of one transceiver block to
the CMU PLLs and receiver CDRs of the other transceiver blocks. In designs that have
channels located in different transceiver blocks, the ITB clock lines eliminate the need
to connect the on-board reference clock crystal oscillator to the refclk pin of each
transceiver block. The ITB clock lines also drive the clock signal on the refclk pins to
the clock logic in the FPGA fabric.
The ITB clock lines also provide an input reference clock path from the refclk pins of
any transceiver block to the ATX PLLs located on the same side of the device.
Each refclk pin drives one ITB clock line for a total of up to eight ITB clock lines on
each of the right and left sides of the device, as shown in
The ITB clock lines provide input reference clock paths from the refclk pins of one
transceiver block to the CMU PLLs and receiver CDRs of other transceiver blocks
located on the same side of the device.
Dedicated CLK Input Pins on the FPGA Global Clock Network
Stratix IV devices provide up to eight differential clock input pins located in
non-transceiver I/O banks that you can use to provide up to eight input reference
clocks to the transceiver blocks. The Quartus
global clock network to route the input reference clock signal from the CLK pins to the
transceiver blocks.
For more information, refer to the “Dedicated Clock Input Pins” section in the
Networks and PLLs in Stratix IV Devices
One global clock resource is available for each CMU PLL, 6G ATX PLL, and receiver
CDR. This allows each CMU PLL, 6G ATX PLL, and receiver CDR to derive its input
reference clock from a separate FPGA CLK input pin.
PCI Express
(HCSL)
Source
refclk
shows an example termination scheme for a reference clock signal when
Rp
Rs
Rs
=
(2)
(2)
50 Ω
Rp
chapter.
=
50 Ω
®
Chapter 2: Transceiver Clocking in Stratix IV Devices
II software automatically chooses the
refclk
refclk
Stratix IV
Figure 2–3 on page
+
-
(Note 1)
February 2011 Altera Corporation
Input Reference Clocking
2–5.
Clock
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