EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 583
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–52. Electrical Idle Inference Conditions
February 2011 Altera Corporation
L0
Recovery.RcvrCfg
Recovery.Speed when
successful speed negotiation
= 1'b1
Recovery.Speed when
successful speed negotiation
= 1'b0
Loopback.Active
(as slave)
LTSSM State
1
Table 1–52
Specification 2.0 and implemented in the Electrical Idle Inference module to infer
electrical idle in various substates of the LTSSM state machine. For the Electrical Idle
Inference Module to correctly infer an electrical idle condition in each LTSSM
substate, you must drive the rx_elecidleinfersel[2:0] signal appropriately, as
shown in
In the Recovery.Speed substate of the LTSSM state machine with unsuccessful speed
negotiation (rx_elecidleinfersel[2:0] = 3'b110), the PCIe Base Specification
requires the receiver to infer an electrical idle condition (pipeelecidle = high) if
absence of an exit from Electrical Idle is detected in a 2000 UI interval for Gen1 data
rate and 16000 UI interval for Gen2 data rate. The electrical idle inference module
detects an absence of exit from Electrical Idle if four /K28.5/ COM code groups are
not received in the specified interval.
In other words, when configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b110, the Electrical Idle Inference module asserts
pipeelecidle high if it does not receive four /K28.5/ COM code groups in a 2000 UI
interval. When configured for Gen1 data rate and
rx_elecidleinfersel[2:0] = 3'b111 in the Loopback.Active substate of the LTSSM
state machine, the Electrical Idle Inference module asserts pipeelecidle high if it
does not receive four /K28.5/ COM code groups in a 128 μs interval.
When configured for Gen2 data rate and rx_elecidleinfersel[2:0] = 3'b110, the
Electrical Idle Inference module asserts pipeelecidle high if it does not receive four
/K28.5/ COM code groups in a 16000 UI interval.
The Electrical Idle Inference module does not have the capability to detect the
electrical idle exit condition based on reception of the electrical idle exit ordered set
(EIEOS), as specified in the PCIe Base Specification.
If you select the Enable Electrical Idle Inference Functionality option in the ALTGX
MegaWizard Plug-In Manager and drive rx_elecidleinfersel[2:0] = 3'b0xx, the
Electrical Idle Inference block uses the EIOS detection from the Fast Recovery
circuitry to drive the pipeelecidle signal.
Absence of skip ordered set in
128 μs window
Absence of TS1 or TS2
ordered set in 1280 UI interval
Absence of TS1 or TS2
ordered set in 1280 UI interval
Absence of an exit from
Electrical Idle in 2000 UI
interval
Absence of an exit from
Electrical Idle in 128 μs
window
Table
lists electrical idle inference conditions specified in the PCIe Base
Gen1 (2.5 Gbps)
1–52.
Absence of skip ordered set in
128 μs window
Absence of TS1 or TS2
ordered set in 1280 UI interval
Absence of TS1 or TS2
ordered set in 1280 UI window
Absence of an exit from
Electrical Idle in 16000 UI
interval
N/A
Gen2 (5 Gbps)
Stratix IV Device Handbook Volume 2: Transceivers
rx_elecidleinfersel[2:0]
3'b111
3'b100
3'b101
3'b101
3'b110
1–139
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