EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 850
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–4
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic
Reconfiguration
Stratix IV Device Handbook Volume 2: Transceivers
ALTGX MegaWizard Plug-In Manager
f
1
Stratix IV GX devices provide two MegaWizard Plug-In Manager interfaces to
support dynamic reconfiguration—ALTGX and ALTGX_RECONFIG.
Use the ALTGX MegaWizard Plug-In manager to enable the dynamic reconfiguration
settings for the transceiver instances.
For more information, refer to the “Reconfiguration Settings” section of the
Transceiver Setup Guide for Stratix IV Devices
The reconfig_clk Clock Requirements for the ALTGX Instance
You must connect the reconfig_clk port to the ALTGX instance in all the
configurations using the dynamic reconfiguration feature.
Table 5–2
instance, based on its configuration.
Table 5–2. Source Clock for the Offset Cancellation Circuit in the ALTGX Instance
Select the reconfig_clk frequency based on the ALTGX configuration shown in
Table
not use dedicated transceiver REFCLK pins or any clocks generated by transceivers.
Altera recommends driving the reconfig_clk signal on a global clock resource. This
clock must be a free-running clock sourced from an I/O clock pin. Do not use
dedicated transceiver refclk pins or any clocks generated by transceivers.
Table 5–3. reconfig_clk Settings for the ALTGX Instance
Note to
(1) The clock source used for offset cancellation must be a free running clock that is not derived from the PLL as this
Note to
(1) The source clock for the offset cancellation circuit in the ALTGX instance must be faster than 37.5 MHz. Offset
Source Clock for the Offset Cancellation Circuit
clock is required for offset cancellation at power up.
cancellation is not required for transmitters and is accomplished using a fixed clock in PCIe mode.
5–3. This clock must be a free-running clock sourced from an I/O clock pin. Do
Figure
Figure
lists the source clock for the offset cancellation circuit in the ALTGX
ALTGX Instance Configuration
5–2:
5–3:
Transmitter only and PCIe
Receiver and Transmitter
reconfig_clk
reconfig_clk
Receiver only
fixedclk
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
chapter.
(1)
reconfig_clk Frequency Range (MHz)
Receiver only and Transmitter only
Receiver and Transmitter
ALTGX Configurations
PCI Express
February 2011 Altera Corporation
2.5
37.5 to 50
37.5 to 50
(1)
to 50
®
(PCIe)
ALTGX
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