EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 682

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix IV Device Handbook Volume 2: Transceivers
Dedicated Left and Right PLL Cascade Network
Stratix IV devices have a dedicated PLL cascade network on the left and right side of
the device that connects to the input reference clock selection multiplexer of the
CMU PLLs, 6G ATX PLLs, and receiver CDRs on the left and right side of the device,
respectively.
The dedicated PLL cascade networks are segmented by bidirectional tri-state buffers
located along the clock line. Segmentation of the dedicated PLL cascade network
allows two or more left and right PLLs to drive the cascade clock line simultaneously.
Because the number of left and right PLLs and transceiver blocks vary from device to
device, the capability of cascading a left and right PLL to the CMU PLLs, 6G ATX
PLLs, and receiver CDRs also varies from device to device.
The following sections describe the Stratix IV GX and GT FPGA fabric-Transceiver
PLLs cascading for the various device packages.
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
February 2011 Altera Corporation