EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 813
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
Figure 4–3. Sample Reset Sequence for Four Transmitter Only Channels
Note to
(1) For t
February 2011 Altera Corporation
Reset and Power-Down Signals
Figure
pll_powerdown
4–3:
Output Status Signals
duration, refer to the
pll_powerdown
Transmitter Only Channel
This configuration contains only a transmitter channel. If you create a Transmitter
Only instance in the ALTGX MegaWizard Plug-In Manager in Basic ×4 functional
mode, use the reset sequence shown in
tx_digitalreset
As shown in
reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset signal asserted during this time period. After you
3. When the transmitter PLL locks, as indicated by the pll_locked signal going high
pll_locked
time between markers 1 and 2).
de-assert the pll_powerdown signal, the transmitter PLL starts locking to the
transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). At this point, the
transmitter is ready for transmitting data.
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
Figure
4–3, for the Transmitter Only channel configuration, follow these
2
3
4
Figure
4–3.
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
pll_powerdown
(the
4–7
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