EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 888

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Table 5–10. rx_dataoutfull[63:0] FPGA Fabric-Transceiver Channel Interface Signal Descriptions (Part 3 of 6)
Stratix IV Device Handbook Volume 2: Transceivers
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA
set to 8/10 bits
16-bit FPGA fabric-transceiver
Channel Interface with PCS-PMA
set to 8/10 bits (continued)
Channel Interface Description
FPGA Fabric-Transceiver
Two 8-bit Data
rx_dataoutfull[7:0] - rx_dataout (LSByte) and rx_dataoutfull[39:32] -
rx_dataout (MSByte)
The following signals are used in 16-bit 8B/10B mode:
Two Control Bits
rx_dataoutfull[8] - rx_ctrldetect (LSB) and rx_dataoutfull[40] -
rx_ctrldetect (MSB)
Two Receiver Error Detect Bits
rx_dataoutfull[9] - rx_errdetect (LSB) and rx_dataoutfull[41]-
rx_errdetect (MSB)
Two Receiver Sync Status Bits
rx_dataoutfull[10] - rx_syncstatus (LSB) and rx_dataoutfull[42]-
rx_syncstatus (MSB)
Two Receiver Disparity Error Bits
rx_dataoutfull[11] - rx_disperr (LSB) and rx_dataoutfull[43] -
rx_disperr (MSB)
Two Receiver Pattern Detect Bits
rx_dataoutfull[12] - rx_patterndetect (LSB) and rx_dataoutfull[44] -
rx_patterndetect (MSB)
rx_dataoutfull[13] and rx_dataoutfull[45]: Rate Match FIFO deletion status
indicator (rx_rmfifodatadeleted) in non-PCIe/PCIe modes
rx_dataoutfull[14] and rx_dataoutfull[46]: Rate Match FIFO insertion status
indicator (rx_rmfifodatainserted) in non-PCIe/PCIe modes
Two 2-bit PCIe Status Bits
rx_dataoutfull[14:13] - rx_pipestatus (LSB) and rx_dataoutfull[46:45]-
rx_pipestatus (MSB)
rx_dataoutfull[15] and rx_dataoutfull[47]: 8B/10B running disparity indicator
(rx_runningdisp)
The following signals are used in 16-bit SONET/SDH mode:
Two 8-bit Data
rx_dataoutfull[7:0] - rx_dataout (LSByte) and rx_dataoutfull[39:32] -
rx_dataout (MSByte)
Two Receiver Alignment Pattern Length Bits
rx_dataoutfull[8] - rx_a1a2sizeout (LSB) and rx_dataoutfull[40]-
rx_a1a2sizeout (MSB)
Two Receiver Sync Status Bits
rx_dataoutfull[10] - rx_syncstatus (LSB) and rx_dataoutfull[42] -
rx_syncstatus (MSB)
Two Receiver Pattern Detect Bits
rx_dataoutfull[12] - rx_patterndetect (LSB) and rx_dataoutfull[44] -
rx_patterndetect (MSB)
Receive Signal Description (Based on Stratix IV GX Supported FPGA
Fabric-Transceiver Channel Interface Widths)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation