EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 533

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–76. 8B/10B Decoder in Single-Width and Double-Width Mode
February 2011 Altera Corporation
Single-Width Mode
datain [19:10]
recovered clock or
recovered clock or
datain[9:0]
tx_clkout[0]
tx_clkout[0]
1
8B/10B Decoder
8B/10B Decoder
Protocols such as PCIe, XAUI, GIGE, and Serial RapidIO require the serial data sent
over the link to be 8B/10B encoded to maintain the DC balance in the serial data
transmitted. These protocols require the receiver PCS logic to implement an 8B/10B
decoder to decode the data before forwarding it to the upper layers for packet
processing.
The Stratix IV GX and GT receiver channel PCS datapaths implement the 8B/10B
decoder after the rate matcher. In functional modes with rate matcher enabled, the
8B/10B decoder receives data from the rate matcher. In functional modes with rate
matcher disabled, the 8B/10B decoder receives data from the word aligner.
The 8B/10B decoder operates in two modes
■
■
The left side of
mode, the 8B/10B decoder receives 10-bit data from the rate matcher or word aligner
(when rate matcher is disabled) and decodes it into an 8-bit data + 1-bit control
identifier. The decoded data is fed to the byte deserializer or the receiver phase
compensation FIFO (if byte deserializer is disabled).
The 8B/10B decoder is compliant to Clause 36 in the IEEE802.3 specification.
8B/10B Decoder
(LSB Byte)
(MSB Byte)
Single-width mode
Double-width mode
8B/10B Decoder in Single-Width Mode
Current Running Disparity
Figure 1–76
rx_errdetect[1]
rx_dataout[7:0]
rx_dataout [15:8]
rx_ctrldetect[1]
rx_ctrldetect
rx_errdetect
rx_disperr[1]
rx_disperr
shows the 8B/10B decoder in single-width mode. In this
datain[19:10]
Double-Width Mode
recovered clock or
recovered clock or
datain[9:0]
tx_clkout[0]
tx_clkout[0]
(Figure
Stratix IV Device Handbook Volume 2: Transceivers
1–76):
8B/10B Decoder
8B/10B Decoder
(LSB Byte)
(MSB Byte)
Current Running Disparity
rx_dataout[15:8]
rx_ctrldetect[1]
rx_errdetect[1]
rx_errdetect
rx_disperr[1]
rx_ctrldetect
rx_dataout[7:0]
rx_disperr
1–89