EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 75
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
February 2011 Altera Corporation
Figure 3–16
behavior in don’t care mode for MLABs.
Figure 3–16. MLABs Same-Port Read-During Write: Don’t Care Mode
For M9K and M144K memory blocks, three output choices are available in same-port
read-during-write mode: “new data” (or flow-through) or “old data”. In new data
mode, the “new data” is available on the rising edge of the same clock cycle on which
it was written. In old data mode, the RAM outputs reflect the “old data” at that
address before the write operation proceeds. In don’t care mode, the RAM outputs
“unknown values” for a read-during-write operation.
Figure 3–17
behavior in new data mode for M9K and M144K blocks.
Figure 3–17. M9K and M144K Blocks Same-Port Read-During-Write: New Data Mode
q(unregistered)
q(registered)
q_a (asyn)
address
bytenna
address
data_in
data_a
rdena
wrena
wrena
clk_a
clk_a
shows sample functional waveforms of same-port read-during-write
shows sample functional waveforms of same-port read-during-write
XX
XX
XX
XX
A0(old data)
A123
01
FFFF
XX23
A0
FFFF
B456
10
0A
B423
FFFF
C789
00
A1(old data)
B423
DDDD
DDDD
AAAA
A1
Stratix IV Device Handbook Volume 1
AAAA
0B
EEEE
11
AAAA
EEEE
FFFF
A2(old data)
XXXX
FFFF
A2
3–19
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