EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 865
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Table 5–5. Transceiver Channel Reconfiguration Modes and .mif Requirements
February 2011 Altera Corporation
Channel and CMU PLL
reconfiguration
Channel reconfiguration with
transmitter PLL select
Central control unit
reconfiguration
Data rate division in transmitter
Note to
(1) Because the transmitter local divider is not available for bonded mode channels, data rate division is supported for non-bonded channels only.
(2) Dynamic reconfiguration from a bonded mode with rate matcher to another bonded mode without rate matcher is not allowed.
Dynamic Reconfiguration
Table
Transceiver Channel Reconfiguration Mode Details
5–5:
Mode
1
(2)
The read transaction in Method 3 is identical to that in Method 2. Refer to
Transaction” on page
Table 5–5
reconfiguration modes available in the ALTGX_RECONFIG MegaWizard Plug-In
Manager.
You cannot dynamically reconfigure from Deterministic Latency mode with the
Enable PLL phase frequency detector (PFD) feedback to compensate latency
uncertainty in Tx dataout and Tx clkout paths relative to the reference clock option
enabled to any other mode with this option disabled. For instance, you cannot
dynamically reconfigure from a CPRI mode to a non-CPRI mode. You can
dynamically change the data rate for CPRI mode.
Read Transaction
lists the supported configurations for the various transceiver channel
Non-bonded configurations of
regular transceiver channels
All configurations of regular
configurations of regular
Basic (PMA Direct) ×1
Basic (PMA Direct) ×N
Basic (PMA Direct) ×1
Basic (PMA Direct) ×N
transceiver channels
transceiver channels
All Transmitter only
×4 bonded mode
×8 bonded mode
configuration
configuration
configuration
configuration
5–16.
To
Supported Configurations
Non-bonded configurations of
regular transceiver channels
All configurations of regular
configurations of regular
transceiver channels
Basic (PMA Direct) ×N
Basic (PMA Direct) ×N
Basic (PMA Direct) ×1
Basic (PMA Direct) ×1
transceiver channels
All Transmitter only
×4 bonded mode
×8 bonded mode
configuration
configuration
configuration
configuration
Stratix IV Device Handbook Volume 2: Transceivers
From
(1)
.mif Requirements
“Read
v
v
v
v
v
v
v
v
—
5–19
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