MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 129
MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
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Refer to the ATD block description chapter for information on the ATDDIEN0 and ATDDIEN1 registers.
During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is
disabled).
3.3.1.1
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the
corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the
associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place
but has no effect on the Port AD pin.
If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 1 (digital input buffer is enabled), a read returns the value of the pin.
Freescale Semiconductor
KWU:
Reset
KWU:
Reset
ATD:
ATD:
W
W
R
R
KWAD15
PTAD15
KWAD7
PTAD7
AN15
AN7
Port AD I/O Register (PTAD)
0
0
7
7
KWAD14
PTAD14
KWAD6
PTAD6
AN14
AN6
0
0
6
6
Figure 3-2. Port AD I/O Register (PTAD)
KWAD13
PTAD13
KWAD5
PTAD5
AN13
AN5
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
5
PTAD12
KWAD4
KWA12
PTAD4
AN12
AN4
0
0
4
4
KWAD11
PTAD11
KWAD3
PTAD3
AN11
AN3
3
0
3
0
Chapter 3 Port Integration Module (PIM9E128V1)
KWAD10
PTAD10
KWAD2
PTAD2
AN10
AN2
0
0
2
2
KWAD9
KWAD1
PTAD9
PTAD1
AN9
AN1
1
0
1
0
KWAD8
KWAD0
PTAD8
PTAD0
AN8
AN0
0
0
0
0
129
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