MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 194
MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 4 Clocks and Reset Generator (CRGV4)
If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all
configuration bits in the register space to its default settings and starts the reset generator. After completing
the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and
the MCU is in run mode again.
If the clock monitor is enabled (CME = 1) the MCU is able to leave pseudo-stop mode when loss of
oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG
generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same
compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the
SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the
interrupt the CRG enters self-clock mode and starts the clock quality checker (see
Section 4.4.4, “Clock
Quality
Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by
SCMIE = 0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo-stop mode.
If any other interrupt source (e.g. RTI) triggers exit from pseudo-stop mode the MCU immediately
continues with normal operation. Because the PLL has been powered-down during stop mode the PLLSEL
bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL
bit again, in order to switch system and core clocks to the PLLCLK.
Table 4-12
summarizes the outcome of a clock loss while in pseudo-stop mode.
MC9S12E128 Data Sheet, Rev. 1.07
194
Freescale Semiconductor
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