MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 181

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency f
4.4.1.1
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK)
is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of
[2 x (SYNR +1)] to output the feedback clock. See
The phase detector then compares the feedback clock, with the reference clock. Correction pulses are
generated based on the phase difference between the two signals. The loop filter then slightly alters the DC
voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the
next subsection. The values of the external filter network and the reference frequency determine the speed
of the corrections and the stability of the PLL.
4.4.1.2
The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the
speed of the lock detector is directly proportional to the final reference frequency. The circuit determines
the mode of the PLL and the lock condition based on this comparison.
Freescale Semiconductor
EXTAL
XTAL
supplied by:
PLL Operation
Acquisition and Tracking Modes
VDDPLL/VSSPLL
VDD/VSS
CONSUMPTION
OSCILLATOR
REDUCED
OSCCLK
MONITOR
CRYSTAL
Figure 4-16. PLL Functional Diagram
MC9S12E128 Data Sheet, Rev. 1.07
PROGRAMMABLE
REFDV <3:0>
REFERENCE
DIVIDER
PROGRAMMABLE
SYN <5:0>
DIVIDER
LOOP
Figure
REFERENCE
FEEDBACK
4-16.
DETECTOR
DETECTOR
FILTER
LOOP
PHASE
LOCK
PDET
Chapter 4 Clocks and Reset Generator (CRGV4)
VDDPLL
DOWN
UP
LOCK
CPUMP
XFC
PIN
VDDPLL/VSSPLL
VCO
PLLCLK
SCM
181
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