MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 297

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

9.5
The reset values of registers and signals are described in the Memory Map and Registers section (see
Section 9.3, “Memory Map and Register
9.6
The SPIV3 only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following
is a description of how the SPIV3 makes a request and how the MCU should acknowledge that request.
The interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF and SPTEF are logically ORed to generate an interrupt request.
9.6.1
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see
changed:
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in
9.6.2
SPIF occurs when new data has been received and copied to the SPI Data Register. After SPIF is set, it
does not clear until it is serviced. SPIF has an automatic clearing process which is described in
Section 9.3.2.4, “SPI Status Register (SPISR).”
the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored
and no new data will be copied into the SPIDR.
9.6.3
SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process which is described in
Status Register (SPISR).”
Freescale Semiconductor
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If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the byte last received from the master before the reset.
Reading from the SPIDR after reset will always read a byte of zeros.
MSTR = 0, The master bit in SPICR1 resets.
Reset
Interrupts
MODF
SPIF
SPTEF
Table
9-3). After MODF is set, the current transfer is aborted and the following bit is
Section 9.3.2.4, “SPI Status Register (SPISR).”
MC9S12E128 Data Sheet, Rev. 1.07
Definition”) which details the registers and their bit-fields.
In the event that the SPIF is not serviced before the end of
Chapter 9 Serial Peripheral Interface (SPIV3)
Section 9.3.2.4, “SPI
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