MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 265

Microcontrollers (MCU) 16 Bit 16MHz

MC9S12E128CPV

Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12E128CPV

Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12E128CPVE
Manufacturer:
FREESCALE
Quantity:
1 560
Part Number:
MC9S12E128CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12E128CPVE
Manufacturer:
FREESCALE
Quantity:
1 560
8.4.5
8.4.5.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
8.4.5.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
Freescale Semiconductor
FROM TXD PIN
OR TRANSMITTER
SCRXD
LOOPS
Receiver
RSRC
RDRF/OR INTERRUPT REQUEST
Receiver Character Length
Character Reception
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
IDLE INTERRUPT REQUEST
CONTROL
LOOP
SBR12–SBR0
CLOCK
BUS
Figure 8-14. SCI Receiver Block Diagram
WAKE
DIVIDER
RAF
BAUD
ILT
RE
PE
PT
M
MC9S12E128 Data Sheet, Rev. 1.07
RECOVERY
DATA
CHECKING
WAKEUP
PARITY
LOGIC
INTERNAL BUS
IDLE
ILIE
RIE
H
Chapter 8 Serial Communication Interface (SCIV3)
11-BIT RECEIVE SHIFT REGISTER
8
7
SCI DATA REGISTER
RDRF
OR
6
5
R8
4
FE
NF
PE
3
2
1
0
L
RWU
265

Related parts for MC9S12E128CPV