MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 443

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

14.3.2
The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual
bits.
14.3.2.1
The VREGCTRL register allows to separately enable features of VREG3V3V2.
14.4
Block VREG3V3V2 is a voltage regulator as depicted in
are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a
low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the
interface to the digital core logic but also manages the operating modes of VREG3V3V2.
14.4.1
VREG3V3V2, respectively its regulator core has two parallel, independent regulation loops (REG1 and
REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only
REG1 providing the supply at V
Freescale Semiconductor
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Functional Description
Register Descriptions
REG — Regulator Core
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
VREG3V3V2 — Control Register (VREGCTRL)
0
0
7
On entering the reduced-power mode the LVIF is not cleared by the
VREG3V3V2.
= Unimplemented or Reserved
Figure 14-2. VREG3V3 — Control Register (VREGCTRL)
0
0
6
DDA
DDA
is above level V
is below level V
DD
Table 14-3. MCCTL1 Field Descriptions
/V
MC9S12E128 Data Sheet, Rev. 1.07
SS
0
0
5
is explained. The principle is also valid for REG2.
LVIA
LVID
and FPM.
or RPM or shutdown mode.
NOTE
0
0
4
Description
Figure
Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
0
0
3
14-1. The regulator functional elements
LVDS
0
2
LVIE
0
1
LVIF
0
0
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