MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 186

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 4 Clocks and Reset Generator (CRGV4)
4.4.5
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. The COP is disabled out of reset. When the COP is being used, software is
responsible for keeping the COP from timing out. If the COP times out it is an indication that the software
is no longer being executed in the intended sequence; thus a system reset is initiated (see
“Computer Operating Properly Watchdog (COP)
Section Figure 4-21., “Clock Chain for
of seven COP time-out periods.
When COP is enabled, the program must write 0x0055 and 0x00AA (in this order) to the ARMCOP
register during the selected time-out period. As soon as this is done, the COP time-out period is restarted.
If the program fails to do this and the COP times out, the part will reset. Also, if any value other than
0x0055 or 0x00AA is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in pseudo-stop mode.
186
Computer Operating Properly Watchdog (COP)
OSCCLK
The clock quality checker enables the PLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running PLL (f
during pseudo-stop mode or wait mode
gating condition
= Clock Gate
STOP(PSTP,PCE),
WAIT(COPWAI),
COP enable
Figure 4-21. Clock Chain for COP
MC9S12E128 Data Sheet, Rev. 1.07
COP”). Three control bits in the COPCTL register allow selection
CR[2:0]
0:0:0
NOTE
Reset).” The COP runs with a gated OSCCLK (see
16384
SCM
4
4
2
2
4
4
) and an active VREG
CR[2:0]
0:1:0
0:1:1
1:1:0
0:0:1
1:0:0
1:0:1
1:1:1
COP TIMEOUT
Freescale Semiconductor
Section 4.5.2,