MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 441

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

14.2
Due to the nature of VREG3V3V2 being a voltage regulator providing the chip internal power supply
voltages most signals are power supply signals connected to pads.
Table 14-1
14.2.1
Signal V
through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
V
For entering shutdown mode, pin V
14.2.2
Signals V
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between V
supply.
Freescale Semiconductor
SSR
V
REGEN
can smoothen ripple on V
V
V
Name
DDR
V
V
V
DDPLL
V
SSPLL
External Signal Description
V
DDA
DDR
DDA
SSA
DD
SS
(optional)
shows all signals of VREG3V3V2 associated with pins.
V
V
is the power input of VREG3V3V2. All currents sourced into the regulator loads flow
DDR
DDA
/V
Check device overview chapter for connectivity of the signals.
SSA
, V
— Regulator Power Input
which are supposed to be relatively quiet are used to supply the analog parts of the
SSA
Port
—
—
—
—
—
—
—
—
— Regulator Reference Supply
Table 14-1. VREG3V3V2 — Signal Properties
DDR
VREG3V3V2 power input (positive supply)
VREG3V3V2 quiet input (positive supply)
VREG3V3V2 quiet input (ground)
VREG3V3V2 primary output (positive supply)
VREG3V3V2 primary output (ground)
VREG3V3V2 secondary output (positive supply)
VREG3V3V2 secondary output (ground)
VREG3V3V2 (Optional) Regulator Enable
DDR
.
MC9S12E128 Data Sheet, Rev. 1.07
should also be tied to ground on devices without a V
NOTE
Function
DDA
and V
Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
SSA
can further improve the quality of this
Reset State
—
—
—
—
—
—
—
—
REGEN
DDR
Pull Up
—
—
—
—
—
—
—
—
pin.
and
441