MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 439

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 14
Dual Output Voltage Regulator (VREG3V3V2)
14.1
The VREG3V3V2 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies
differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up
to 5 V (typical).
14.1.1
The block VREG3V3V2 includes these distinctive features:
14.1.2
There are three modes VREG3V3V2 can operate in:
Freescale Semiconductor
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Two parallel, linear voltage regulators
— Bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR)
Low-voltage reset (LVR)
Full-performance mode (FPM) (MCU is not in stop mode)
The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing
capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR
(power-on reset) are available.
Reduced-power mode (RPM) (MCU is in stop mode)
The purpose is to reduce power consumption of the device. The output voltage may degrade to a
lower value than in full-performance mode, additionally the current sourcing capability is
substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled.
Shutdown mode
Controlled by V
This mode is characterized by minimum power consumption. The regulator outputs are in a high
impedance state, only the POR feature is available, LVD and LVR are disabled.
This mode must be used to disable the chip internal regulator VREG3V3V2, i.e., to bypass the
VREG3V3V2 to use external supplies.
Introduction
Features
Modes of Operation
REGEN
(see device overview chapter for connectivity of V
MC9S12E128 Data Sheet, Rev. 1.07
REGEN
).
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