MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 480

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 16 Debug Module (DBGV1)
16.3.2.1
480
TRGSEL
DBGEN
Reset
BEGIN
Field
ARM
7
6
5
4
W
R
DBGEN
DBG Mode Enable Bit — The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be
set if the MCU is in secure mode.
0 DBG mode disabled
1 DBG mode enabled
Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See
Section 16.4.2.4, “Arming the DBG
0 Debugger unarmed
1 Debugger armed
Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for comparators A and B in DBG
mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See
Section 16.4.2.1.2, “Trigger
based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to
“Breakpoint Based on Comparator A and
0 Trigger on any compare address match
1 Trigger before opcode at compare address gets executed (tagged-type)
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace
buffer. See
for more details.
0 Trigger at end of stored data
1 Trigger before storing data
Debug Control Register 1 (DBGC1)
0
7
All bits are used in DBG mode only.
This register cannot be written if BKP mode is enabled (BKABEN in
DBGC2 is set).
to DBGEN[7:6] will be interpreted as a write of 00.
= Unimplemented or Reserved
Section 16.4.2.8.1, “Storing with
ARM
0
6
Figure 16-4. Debug Control Register (DBGC1)
Table 16-3. DBGC1 Field Descriptions
TRGSEL
Selection,” for more information. TRGSEL may also determine the type of breakpoint
MC9S12E128 Data Sheet, Rev. 1.07
0
5
Module,” for more information.
B.”
BEGIN
NOTE
NOTE
Begin-Trigger,” and
0
4
Description
DBGBRK
0
3
Section 16.4.2.8.2, “Storing with
0
0
2
Freescale Semiconductor
Section 16.4.3.1,
0
1
CAPMOD
End-Trigger,”
0
0