MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 488
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MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12E128CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 16 Debug Module (DBGV1)
16.3.2.8
1
2
488
BKAMB[H:L]
In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0’s.
In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
RWCEN
Reset
Field
RWC
Field
7:6
1
0
W
R
BKAMBH
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for comparator C. RWCEN is not useful for tagged breakpoints.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Breakpoint Mask High Byte for First Address — In dual or full mode, these bits may be used to mask (disable)
the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in
Table
The x:0 case is for a full address compare. When a program page is selected, the full address compare will be
based on bits for a 20-bit compare. The registers used for the compare are {DBGCAX[5:0], DBGCAH[5:0],
DBGCAL[7:0]}, where DBGAX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU
address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit
compare. The registers used for the compare are {DBGCAH[7:0], DBGCAL[7:0]} which corresponds to CPU
address [15:0].
Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several
The 1:0 case is not sensible because it would ignore the high order address and compare the low order and
expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKAMBH
control bit).
The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes
sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCAX compares.
Debug Control Register 3 (DBGC3)
0
7
16-16.
physical addresses may match with a single logical address. This problem may be avoided by using DBG
mode to generate breakpoints.
1
BKAMBL
0
6
Table 16-14. DBGC2 Field Descriptions (continued)
Figure 16-14. Debug Control Register 3 (DBGC3)
1
Table 16-15. DBGC3 Field Descriptions
BKBMBH
MC9S12E128 Data Sheet, Rev. 1.07
0
5
2
BKBMBL
0
4
Description
Description
2
RWAEN
0
3
RWA
0
2
RWBEN
Freescale Semiconductor
0
1
RWB
0
0
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