MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 556

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 19 Module Mapping Control (MMCV4)
of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages
all CPU read data bus swapping operations.
19.4.2
As data flows on the core address bus, the MMC decodes the address information, determines whether the
internal core register or firmware space, the peripheral space or a memory register or array space is being
addressed and generates the correct select signal. This decoding operation also interprets the mode of
operation of the system and the state of the mapping control registers in order to generate the proper select.
The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip
select (XCS).
19.4.2.1
Although internal resources such as control registers and on-chip memory have default addresses, each can
be relocated by changing the default values in control registers. Normally, I/O addresses, control registers,
vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not
overlap. The MMC will make only one select signal active at any given time. This activation is based upon
the priority outlined in
signal for the block with the highest priority will become active. An example of this is if the registers and
the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of
RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority.
This means that registers, vectors, and on-chip memory are always visible to a program regardless of the
values in the page select registers.
In expanded modes, all address space not used by internal resources is by default external memory space.
The data registers and data direction registers for ports A and B are removed from the on-chip memory
map and become external accesses. If the EME bit in the MODE register (see MEBI block description
chapter) is set, the data and data direction registers for port E are also removed from the on-chip memory
map and become external accesses.
In special peripheral mode, the first 16 registers associated with bus expansion are removed from the
on-chip memory map (PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, MODE, PUCR,
RDRIV, and the EBI reserved registers).
556
Address Decoding
Select Priority and Mode Considerations
Table
Priority
Highest
Lowest
...
...
...
...
19-15. If two or more blocks share the same address space, only the select
Table 19-15. Select Signal Priority
MC9S12E128 Data Sheet, Rev. 1.07
BDM (internal to core) firmware or register space
Remaining external space
EEPROM memory block
On-chip FLASH or ROM
Internal register space
RAM memory block
Address Space
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