MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 462
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MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12E128CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 15 Background Debug Module (BDMV4)
clock cycle earlier. Synchronization between the host and target is established in this manner at the start
of every bit time.
Figure 15-7
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally
driven signals.
The receive cases are more complicated.
system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
462
START OF BIT TIME
TARGET SYSTEM
TRANSMIT 1
TRANSMIT 0
PERCEIVED
CLOCK
HOST
HOST
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
SYNCHRONIZATION
UNCERTAINTY
Figure 15-7. BDM Host-to-Target Serial Bit Timing
MC9S12E128 Data Sheet, Rev. 1.07
Figure 15-8
10 CYCLES
TARGET SENSES BIT
shows the host receiving a logic 1 from the target
Freescale Semiconductor
EARLIEST
START OF
NEXT BIT
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