MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 557

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

In emulation modes, if the EMK bit in the MODE register (see MEBI block description chapter) is set, the
data and data direction registers for port K are removed from the on-chip memory map and become
external accesses.
19.4.2.2
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 7 is used
as an active-low emulation chip select signal, ECS. This signal is active when the system is in emulation
mode, the EMK bit is set and the FLASH or ROM space is being addressed subject to the conditions
outlined in
EMK bit is clear, this pin is used for general purpose I/O.
19.4.2.3
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 6 is used
as an active-low external chip select signal, XCS. This signal is active only when the ECS signal described
above is not active and when the system is addressing the external address space. Accesses to
unimplemented locations within the register space or to locations that are removed from the map (i.e., ports
A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this
pin is used for general purpose I/O.
19.4.3
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
in the physical memory space. The paged memory space can consist of solely on-chip memory or a
combination of on-chip and off-chip memory. This partitioning is configured at system integration through
the use of the paging configuration switches (pag_sw1:pag_sw0) at the core boundary. The options
available to the integrator are as given in
for easy reference).
Based upon the system configuration, the program page window will consider its access to be either
internal or external as defined in
Freescale Semiconductor
Section 19.4.3.2, “Extended Address (XAB19:14) and ECS Signal
Memory Expansion
Emulation Chip Select Signal
External Chip Select Signal
pag_sw1:pag_sw0
00
01
10
11
Table 19-16. Allocated Off-Chip Memory Options
Table
MC9S12E128 Data Sheet, Rev. 1.07
19-17.
Table 19-16
Off-Chip Space
876K bytes
768K bytes
512K bytes
0K byte
(this table matches
Chapter 19 Module Mapping Control (MMCV4)
Table 19-12
On-Chip Space
128K bytes
256K bytes
512K bytes
1M byte
Functionality.” When the
but is repeated here
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